Reducing Migration-induced Misses in an over-Subscribed Multiprocessor System

REZA, SAJJID. Reducing Migration-induced Misses in an Over-Subscribed Multiprocessor System. (Under the direction of Prof. Gregory T. Byrd.) In a large multiprocessor server platform, using multicore chips, the scheduler often migrates a scheduling entity, i.e. a thread or process or virtual machine, in order to achieve better load balancing or ensure fairness among competing scheduling entities. Similar to a context switch, each such migration incurs overhead, from saving and restoring processor states and virtual machine control structure, extra Translation Look aside Buffer (TLB) misses and related page walks, cache misses, and interrupt rerouting. Such migration impact is likely to be more severe in virtualized environments, where high over-subscription of CPUs is very common for server consolidation workloads or virtual desktop infrastructure deployment causing frequent migrations and context switches. One way to mitigate such overhead would be to constrain a thread or virtual CPU to be executed on a specific CPU only. However, this approach will likely cause load imbalance, and would still suffer from context switch related misses. Furthermore, effectively determining and managing such constrain assignments of threads to CPUs would not be a trivial task and is unrealistic particularly in a large data center with thousands of servers running varieties of workloads. Alternatively, if we could effectively preserve important footprints (both cache and TLB) and reload them with migration of the process, we could avoid the expensive misses. We characterized the effectiveness of saving and restoring TLB cache entries over a context switch/migration and we found that 60-100% of TLB cache misses could be avoided. We also present two predictors to select TLB entries that are most likely to be reused. After comprehensive evolution, we found that both predictors could reduce storage footprints by 20-80% for most workloads while keeping the false negative rate very low. We also characterized the effectiveness of preserving cache in particular L2 where working set of a process/VM resides, in reducing the migration-induced cache misses. We propose three different MRU based schemes (local, regional and global) to select cache tags to be prefetched following a migration. After comprehensive evolution we found that the simple MRU (most recently used) based selection can provide similar benefit as more complex and costly (in terms of hardware implementation) global or regional MRU schemes and can provide performance benefits of 1.5% -27% reduction in CPI (cycles per instruction) following a migration. We also compared our migration prefetcher with standard hardware stream-based and stride-based prefetchers and found that our migration prefetcher performs almost always better. In some cases, combining the migration prefetcher with a standard hardware prefetcher can provide significant further improvements. © Copyright 2012 by Sajjid Reza All Rights Reserved Reducing Migration-induced Misses in an Over-Subscribed Multiprocessor System